A well known problem in the manufacturing of electronic circuit boards is early failures which are referred to as infant failures. Statistically, the majority of the electrical devices that will fail in the first ten years will fail during the first year of operation. To reduce these failures and associated warranty cost, manufacturers perform burn-in tests. Such tests can eliminate the majority of the electrical devices that will fail during the first year of operation. During a burn-in test, the devices are subjected to elevated thermal or electrical operating conditions for a long period of time, typically, one to eight weeks, thereby simulating one year of operation under normal conditions.
In the prior art, U.S. Pat. No. 5,187,432 stresses assembled circuit boards well beyond normal operational limits both with respect to supply voltages and temperature cycling. The circuit boards are transferred between a cold bath of inert liquid and a hot bath of inert liquid while the power voltages are being applied for short periods of time at voltages which may exceed the normal voltages of the devices. The circuit boards are transferred rapidly between the hot bath to the cold bath and vice versa and maximum stresses are achieved without damaging parts or circuit boards.
Whereas the testing method set forth in U.S. Pat. No. 5,187,432 performs the functions of a burn-in test, there still exists a class of flaws which can only be accelerated into observable failures by doing mechanical vibration stressing. Prior art mechanical vibration stressing has consisted of placing equipment on mechanical shaker tables and mechanically moving the whole electrical apparatus. Whereas such vibration testing does perform the mechanical vibration stressing, it is not compatible with high velocity manufacturing and just-in-time (JIT) processes. The JIT process requires that the various parts needed to build a complex piece of electronic gear such as a modern telecommunications system arrive at the manufacturing plant almost simultaneously and that the complete electronic system is produced in a matter of days, often as short as four or five days. Since a large amount of time is required to assemble circuit boards, there is a limit on how many different stages of testing can be performed. Each additional stage introduced into the JIT process adds to the delay in producing the final product. In addition, the JIT process requires that individual components of the electronic system be tested separately. The most complex component in the electronic system is the printed circuit packs. Prior art vibration techniques of testing each circuit pack individually on shaker tables would cause additional delays.
Hence, there exists a long felt need among electronic system manufacturers for a method that combines burn-in and vibration testing in a simple integrated testing method.